CCD imagers of the field transfer type have an image register comprising an array of parallelled charge transfer channels in which charge packets are accumulated during image integration time intervals. The charge that is accumulated is generated by photoconversion of elements of a radiant energy image impinging upon the array. During the integration time intervals it is common practice to apply static clocking signals to a plurality of gate electrodes arranged in succession across the parallelled charge transfer channels of the image register, to define boundaries for the image elements. These imagers also have a field storage register comprising an array of parallelled charge transfer channels shielded from radiant energy, with gate electrodes arranged in succession across the parallelled charge transfer channels thereof.
During field transfer intervals, the charge packets representative of the intensity of respective image elements are transferred from the parallelled charge transfer channels of the image register to respective ones of the parallelled charge transfer channels of the field storage register. This is done by applying dynamic clocking signals to the gate electrodes of the image and field storage registers, to operate the charge transfer channels of the image register as CCD shift registers to supply lines of charge packets in parallel at their output ends, and to operate the charge transfer channels of the field storage register as CCD shift registers to receive respective ones of the charge packets at their input ends. That is, each charge transfer channel in the image register and a corresponding charge transfer channel in the field storage register following are operated as a cascade connection of CCD shift registers. The rate of dynamic clocking of the image and field storage registers during these field transfer times is generally relatively high, so that complete transfer of a field of charge packets representative of image element intensity can be carried out during field retrace times.
During the ensuing field trace time the image register again receives static clocking signal; and at least a portion, if not all, of the field trace time is included in the next image integration time interval. In the field trace time lines of charge packets are advanced a row at a time during line retrace time through the field storage register. The line of charge packets transferred in parallel out of the field storage register charge transfer channel each line retrace time is converted by an output line register to appear serially in time during the ensuing line trace time.
Until now the standard diagonal dimension of the image register in a CCD imager designed for broadcast television camera use has been eight millimeters and three phase clocking of a 480 lines or so image register has kept gate electrode length below the seven microns or so maximum associated with acceptable graininess of the CCD imager video output signal. There is a strong commercial impetus, however, to develop CCD imagers with eleven millimeters diagonal dimension so the same camera optics could be used that has been developed for vidicons. The larger image elements require that the number of clocking phases in the image register be increased so that gate electrode length can be held to the seven micron maximum to avoid excessive graininess. It would be preferable to increase the number of clock phases to an even number, such as four or six, to implement providing perfect line interlace between alternate field scans.
In prior art CCD imagers of field transfer type the synchronous clocking of the image and field storage registers has been implemented by clocking the registers with the same number of clocking phases. E.g., in the broadcast camera CCD imagers both the image and field storage registers use three-phase clocking, wherein every third gate electrode in the succession of gate electrodes spanning the parallelled charge transfer channels of an array CCD register receives the same phase of clocking signal, lagging the phase of clocking signal received by the preceding gate electrode, and leading the phase of clocking signal received by the succeeding gate electrode.
However, while it is a practical necessity to increase the number of phases of clocking signal applied to the image register upwards from three, it would be preferable not to have to increase the number of phases of clocking signal applied to the field storage register from three. This preference arises from the desire to avoid the problems of having to bus the extra clocking phases across the CCD imager.
The field storage register, unlike the image register, normally does not have anti-blooming drains between its charge transfer channels. So the charge transfer channels in the field storage register can be made wider than those in the image register. Accordingly, when this is done the dynamic range of equal length charge transfer stages (directly related to charge storage capabilities of the stages) is greater in a three-phase field storage register than in a three-phase image register.
Increasing the number of clocking phases in the image register makes the two phases of clocking, which must at times be simultaneously erecting barrier potentials in the image register to implement forward transfer of charge, a smaller portion of the total number of clocking phases. This plus the fact that pixel size is increased for given gate electrode length, if the number of gate electrodes per charge transfer stage is increased, increases the dynamic range of the image register vis-a-vis the three-phase field storage register. Matching the dynamic ranges of the image and field storage register charge transfer stages provides a better imager sensitivity for given area on the semiconductor die.